From 6e9509d1a8f71ba6b5bf96440e155d25dca731b6 Mon Sep 17 00:00:00 2001 From: Frederick Yin Date: Wed, 24 Aug 2022 14:13:00 +0800 Subject: projects/nand2tetris_1: rename img dir to nand2tetris_1 --- docs/projects/img/nand2tetris/6502.jpg | Bin 235588 -> 0 bytes docs/projects/img/nand2tetris/alu.kra | Bin 507037 -> 0 bytes docs/projects/img/nand2tetris/alu.png | Bin 122130 -> 0 bytes docs/projects/img/nand2tetris/alu_highlighted.png | Bin 93144 -> 0 bytes docs/projects/img/nand2tetris/and_gate.png | Bin 11081 -> 0 bytes docs/projects/img/nand2tetris/and_gate_nand.png | Bin 17995 -> 0 bytes .../projects/img/nand2tetris/and_gate_nand_not.png | Bin 16708 -> 0 bytes docs/projects/img/nand2tetris/computer.kra | Bin 460149 -> 0 bytes .../img/nand2tetris/computer_registers.png | Bin 143235 -> 0 bytes docs/projects/img/nand2tetris/cpu.kra | Bin 841631 -> 0 bytes docs/projects/img/nand2tetris/cpu.png | Bin 222785 -> 0 bytes docs/projects/img/nand2tetris/cpu_book.png | Bin 170476 -> 0 bytes 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b/docs/projects/img/nand2tetris_1/register.png new file mode 100644 index 0000000..ff32d3c Binary files /dev/null and b/docs/projects/img/nand2tetris_1/register.png differ diff --git a/docs/projects/img/nand2tetris_1/register_internal.png b/docs/projects/img/nand2tetris_1/register_internal.png new file mode 100644 index 0000000..f9ef91e Binary files /dev/null and b/docs/projects/img/nand2tetris_1/register_internal.png differ diff --git a/docs/projects/img/nand2tetris_1/zx_nx.png b/docs/projects/img/nand2tetris_1/zx_nx.png new file mode 100644 index 0000000..14330a2 Binary files /dev/null and b/docs/projects/img/nand2tetris_1/zx_nx.png differ diff --git a/docs/projects/nand2tetris_1.md b/docs/projects/nand2tetris_1.md index 865595d..42337f3 100644 --- a/docs/projects/nand2tetris_1.md +++ b/docs/projects/nand2tetris_1.md @@ -44,18 +44,18 @@ CHIP And { Graphically, the HDL describes the following schematic: -![A NAND connected to a NOT](img/nand2tetris/and_gate_nand_not.png) +![A NAND connected to a NOT](img/nand2tetris_1/and_gate_nand_not.png) Here `a`, `b` and `out` are hardcoded, but `nout` is an arbitrary name I gave to the internal pin. If we further substitute the implementation of `Not` in `Nand`, this is what _actually_ lives on the silicon: -![Two NANDs](img/nand2tetris/and_gate_nand.png) +![Two NANDs](img/nand2tetris_1/and_gate_nand.png) Once we have written this HDL code, we can encapsulate the AND gate in the following symbol, which is in essence two NAND gates in a trenchcoat: -![One AND](img/nand2tetris/and_gate.png) +![One AND](img/nand2tetris_1/and_gate.png) And this is one of the few chips that have so few pins exposed (hence "elementary") that you can craft a truth table for it, and thus can test @@ -182,7 +182,7 @@ this call for an `if` statement? Well, in project 01 I made a chip named `Mux16` and it is _tremendously_ helpful. It's the hardware embodiment of `if () ... else ...`. -![Schematic of a mux](img/nand2tetris/mux.png) +![Schematic of a mux](img/nand2tetris_1/mux.png) (In reality we are using the 16-bit version, but in principle they're the same.) @@ -200,7 +200,7 @@ Mux16(a=zdx, b=ndx, sel=nx, out=px); Graphically: -![Two muxes in series outputting "px"](img/nand2tetris/zx_nx.png) +![Two muxes in series outputting "px"](img/nand2tetris_1/zx_nx.png) (The order of the muxes matters, because when `zx = nx = 1`, this logic configuration yields `~0 = -1` while the other way gives you 0.) @@ -254,7 +254,7 @@ set iff every bit in `out` is zero. That's it, we have completed the ALU! I know y'all are anticipating the schematics; how can I let you down? -![Schematic of ALU](img/nand2tetris/alu.png) +![Schematic of ALU](img/nand2tetris_1/alu.png) For some reason nand2tetris only provided me with `Or8Way`, which OR's together 8 bits, so I had to use two of them to do all 16. I tried writing @@ -363,7 +363,7 @@ boolean AND and binary addition. It is the Mux's job to select which branch to pass downstream, and which one to discard. This is, in a stretch, called [speculative execution](https://en.wikipedia.org/wiki/Speculative_execution) -![Schematic of ALU. The AND, Adder, and "f" mux are highlighted](../img/nand2tetris/alu_highlighted.png) +![Schematic of ALU. The AND, Adder, and "f" mux are highlighted](img/nand2tetris_1/alu_highlighted.png) As you see in the highlighted area, _both_ of these gates are switching internally, and both of them consume power, even when one of @@ -400,7 +400,7 @@ can build registers from 1 bit to 16K words. Here's how a register works from the user's point of view: -![Schematic of chip with in, load, and out pins](img/nand2tetris/register.png) +![Schematic of chip with in, load, and out pins](img/nand2tetris_1/register.png) If you give it some data via `in` and pull `load` to logic one, the data will show up in `out` at the next clock cycle. However as long as `load` @@ -413,7 +413,7 @@ into the DFF again, creating an eternal feedback loop, but this time the simulator handles it with no problem, because the loop is delayed by one clock cycle each step. -![Schematic of Mux and DFF in register](img/nand2tetris/register_internal.png) +![Schematic of Mux and DFF in register](img/nand2tetris_1/register_internal.png) The RAM I proceeded to build is just an array of arrays of arrays of … of arrays of registers. Just copy and paste; no thinking required. @@ -430,7 +430,7 @@ zero. It's not hard to think of using the Register for storage and Inc16 (16-bit incrementer) to do the math. The rest is Muxes, just like this: -![PC with "out" wired to output of the final "reset" mux](img/nand2tetris/pc_incorrect.png) +![PC with "out" wired to output of the final "reset" mux](img/nand2tetris_1/pc_incorrect.png) There is a problem with this solution. Do you see it? Let's read the chip specs again carefully: @@ -450,7 +450,7 @@ We just need a way to delay `out` by one clock cycle. The only sequential chip here is the Register, so let's try hooking `out` onto its output instead: -![PC with "out" wired to output of Register](img/nand2tetris/pc.png) +![PC with "out" wired to output of Register](img/nand2tetris_1/pc.png) Simulation tells me that this works perfectly, but deep inside I feel I'm still extremely sloppy at clocked logic. @@ -464,7 +464,7 @@ instructions. But first, we need to imagine we have a computer. ![Incomplete schematic of computer. Inside blue rectangle: ROM, CPU, RAM. Inside the CPU is a blob labeled "ALU and stuff", A Register, and D Register. -Outside: Reset button, screen, keyboard.](img/nand2tetris/computer_registers.png) +Outside: Reset button, screen, keyboard.](img/nand2tetris_1/computer_registers.png) Here you see three devices inside the blue rectangle: ROM, CPU, and RAM. @@ -599,7 +599,7 @@ which is 24576. If you write the highest bit to one in RAM[16384], you paint the top left pixel black. If you press space, it sets RAM[24576] to 32 (0x20). You can interact with them in the CPU emulator. -!["Pong" running in the CPU emulator](img/nand2tetris/cpu_emulator_pong.png) +!["Pong" running in the CPU emulator](img/nand2tetris_1/cpu_emulator_pong.png) ▲ CPU Emulator running Pong @@ -658,7 +658,7 @@ The instant I read the requirements, I knew there will be a ton of internal wires. Fortunately, the authors provided a block diagram similar to this one: -![Incomplete diagram of CPU. Many labels are question marks](img/nand2tetris/cpu_book.png) +![Incomplete diagram of CPU. Many labels are question marks](img/nand2tetris_1/cpu_book.png) Yikes! What's with the question marks? Apparently it's the authors' own version of spoiler alerts. I had to figure out what they are by myself, @@ -707,7 +707,7 @@ four groups of control bits: In a hunch, it seems we have the answer to most of the question marks. -![CPU but some question marks are replaced with bit names](img/nand2tetris/cpu_hunch.png) +![CPU but some question marks are replaced with bit names](img/nand2tetris_1/cpu_hunch.png) This is simple but wrong. Let's take a close look at the `load` pin labeled `d1` on the A register. If we try to load address 1 into it, using @@ -727,7 +727,7 @@ The mux on the left will let the instruction through because `opcode` is load, because `instruction[5]` is zero. Something similar will also happen to `d2` and `d3`, so we add a little logic: -![CPU with correct logic controls at d1, d2, and d3](img/nand2tetris/cpu_controls.png) +![CPU with correct logic controls at d1, d2, and d3](img/nand2tetris_1/cpu_controls.png) This ensures that A, D and M load data if and only if we explicitly tell them to. Now we shift our attention to the only two question marks left: @@ -738,12 +738,12 @@ that we can set the PC to its input if we pull `load` to high, and this way we can jump to ROM[A]. But how? ![CPU with a blob labeled "mysterious logic that decides whether we jump -or not"](img/nand2tetris/cpu_mysterious_jump_logic.png) +or not"](img/nand2tetris_1/cpu_mysterious_jump_logic.png) It's actually very straightforward! Apparently the authors thought it through when specifying the ALU. -![Complete diagram of CPU](img/nand2tetris/cpu.png) +![Complete diagram of CPU](img/nand2tetris_1/cpu.png) (Actual gates may differ) @@ -920,7 +920,7 @@ this deep-rooted fear that one loose jumper wire on the breadboard can knock your Ben Eater-style computer completely off the rail? ![DIP chips and LCD connected with numerous jumper wires on three -breadboards; the LCD reads "6502 Computer kit"](img/nand2tetris/6502.jpg) +breadboards; the LCD reads "6502 Computer kit"](img/nand2tetris_1/6502.jpg) ▲ Image credit: [Ben Eater, "Build a 6502 computer"](https://eater.net/6502) -- cgit v1.2.3