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-rw-r--r--projects/demo/Xor.cmp5
-rw-r--r--projects/demo/Xor.hdl25
-rw-r--r--projects/demo/Xor.out0
-rw-r--r--projects/demo/Xor.tst29
4 files changed, 59 insertions, 0 deletions
diff --git a/projects/demo/Xor.cmp b/projects/demo/Xor.cmp
new file mode 100644
index 0000000..a1e07b2
--- /dev/null
+++ b/projects/demo/Xor.cmp
@@ -0,0 +1,5 @@
+| a | b | out |
+| 0 | 0 | 0 |
+| 0 | 1 | 1 |
+| 1 | 0 | 1 |
+| 1 | 1 | 0 |
diff --git a/projects/demo/Xor.hdl b/projects/demo/Xor.hdl
new file mode 100644
index 0000000..db49351
--- /dev/null
+++ b/projects/demo/Xor.hdl
@@ -0,0 +1,25 @@
+// This file is part of www.nand2tetris.org
+// and the book "The Elements of Computing Systems"
+// by Nisan and Schocken, MIT Press.
+// File name: projects/demo/Xor.hdl
+
+/**
+ * Exclusive-or gate: true if either a is true and b is false, or
+ * a is false and b is true; false otherwise.
+ * QUESTION: how can the simulator execute this program properly without
+ * HDL implementations of the underlying Not, And, and Or chip-parts?
+ * Answer: since the demo folder contains no Not.hdl, And.hdl and Or.hdl
+ * files, the simulator reverts to using their built-in implementations.
+ */
+
+CHIP Xor {
+ IN a, b;
+ OUT out;
+
+ PARTS:
+ Not (in=a, out=nota);
+ Not (in=b, out=notb);
+ And (a=a, b=notb, out=x);
+ And (a=nota, b=b, out=y);
+ Or (a=x, b=y, out=out);
+} \ No newline at end of file
diff --git a/projects/demo/Xor.out b/projects/demo/Xor.out
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/projects/demo/Xor.out
diff --git a/projects/demo/Xor.tst b/projects/demo/Xor.tst
new file mode 100644
index 0000000..658cbe5
--- /dev/null
+++ b/projects/demo/Xor.tst
@@ -0,0 +1,29 @@
+// This file is part of www.nand2tetris.org
+// and the book "The Elements of Computing Systems"
+// by Nisan and Schocken, MIT Press.
+// File name: projects/01/Xor.tst
+
+load Xor.hdl,
+output-file Xor.out,
+compare-to Xor.cmp,
+output-list a%B3.1.3 b%B3.1.3 out%B3.1.3;
+
+set a 0,
+set b 0,
+eval,
+output;
+
+set a 0,
+set b 1,
+eval,
+output;
+
+set a 1,
+set b 0,
+eval,
+output;
+
+set a 1,
+set b 1,
+eval,
+output;