From 9542deeb483a00b6fabed7574720926ce97d7511 Mon Sep 17 00:00:00 2001 From: Frederick Yin Date: Tue, 16 Aug 2022 11:54:23 +0800 Subject: Projects, 01-06 completed --- projects/03/a/RAM64.hdl | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 projects/03/a/RAM64.hdl (limited to 'projects/03/a/RAM64.hdl') diff --git a/projects/03/a/RAM64.hdl b/projects/03/a/RAM64.hdl new file mode 100644 index 0000000..e6f4094 --- /dev/null +++ b/projects/03/a/RAM64.hdl @@ -0,0 +1,28 @@ +// This file is part of www.nand2tetris.org +// and the book "The Elements of Computing Systems" +// by Nisan and Schocken, MIT Press. +// File name: projects/03/a/RAM64.hdl + +/** + * Memory of 64 registers, each 16 bit-wide. Out holds the value + * stored at the memory location specified by address. If load==1, then + * the in value is loaded into the memory location specified by address + * (the loaded value will be emitted to out from the next time step onward). + */ + +CHIP RAM64 { + IN in[16], load, address[6]; + OUT out[16]; + + PARTS: + DMux8Way(in=load, sel=address[3..5], a=l0, b=l1, c=l2, d=l3, e=l4, f=l5, g=l6, h=l7); + RAM8(in=in, load=l0, address=address[0..2], out=o0); + RAM8(in=in, load=l1, address=address[0..2], out=o1); + RAM8(in=in, load=l2, address=address[0..2], out=o2); + RAM8(in=in, load=l3, address=address[0..2], out=o3); + RAM8(in=in, load=l4, address=address[0..2], out=o4); + RAM8(in=in, load=l5, address=address[0..2], out=o5); + RAM8(in=in, load=l6, address=address[0..2], out=o6); + RAM8(in=in, load=l7, address=address[0..2], out=o7); + Mux8Way16(a=o0, b=o1, c=o2, d=o3, e=o4, f=o5, g=o6, h=o7, sel=address[3..5], out=out); +} -- cgit v1.2.3