From 9542deeb483a00b6fabed7574720926ce97d7511 Mon Sep 17 00:00:00 2001 From: Frederick Yin Date: Tue, 16 Aug 2022 11:54:23 +0800 Subject: Projects, 01-06 completed --- projects/03/b/RAM16K.hdl | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 projects/03/b/RAM16K.hdl (limited to 'projects/03/b/RAM16K.hdl') diff --git a/projects/03/b/RAM16K.hdl b/projects/03/b/RAM16K.hdl new file mode 100644 index 0000000..f981555 --- /dev/null +++ b/projects/03/b/RAM16K.hdl @@ -0,0 +1,24 @@ +// This file is part of www.nand2tetris.org +// and the book "The Elements of Computing Systems" +// by Nisan and Schocken, MIT Press. +// File name: projects/03/b/RAM16K.hdl + +/** + * Memory of 16K registers, each 16 bit-wide. Out holds the value + * stored at the memory location specified by address. If load==1, then + * the in value is loaded into the memory location specified by address + * (the loaded value will be emitted to out from the next time step onward). + */ + +CHIP RAM16K { + IN in[16], load, address[14]; + OUT out[16]; + + PARTS: + DMux4Way(in=load, sel=address[12..13], a=l0, b=l1, c=l2, d=l3); + RAM4K(in=in, load=l0, address=address[0..11], out=o0); + RAM4K(in=in, load=l1, address=address[0..11], out=o1); + RAM4K(in=in, load=l2, address=address[0..11], out=o2); + RAM4K(in=in, load=l3, address=address[0..11], out=o3); + Mux4Way16(a=o0, b=o1, c=o2, d=o3, sel=address[12..13], out=out); +} -- cgit v1.2.3