From 9542deeb483a00b6fabed7574720926ce97d7511 Mon Sep 17 00:00:00 2001 From: Frederick Yin Date: Tue, 16 Aug 2022 11:54:23 +0800 Subject: Projects, 01-06 completed --- projects/05/CPU.hdl | 74 +++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 74 insertions(+) create mode 100644 projects/05/CPU.hdl (limited to 'projects/05/CPU.hdl') diff --git a/projects/05/CPU.hdl b/projects/05/CPU.hdl new file mode 100644 index 0000000..71dbd72 --- /dev/null +++ b/projects/05/CPU.hdl @@ -0,0 +1,74 @@ +// This file is part of www.nand2tetris.org +// and the book "The Elements of Computing Systems" +// by Nisan and Schocken, MIT Press. +// File name: projects/05/CPU.hdl + +/** + * The Hack CPU (Central Processing unit), consisting of an ALU, + * two registers named A and D, and a program counter named PC. + * The CPU is designed to fetch and execute instructions written in + * the Hack machine language. In particular, functions as follows: + * Executes the inputted instruction according to the Hack machine + * language specification. The D and A in the language specification + * refer to CPU-resident registers, while M refers to the external + * memory location addressed by A, i.e. to Memory[A]. The inM input + * holds the value of this location. If the current instruction needs + * to write a value to M, the value is placed in outM, the address + * of the target location is placed in the addressM output, and the + * writeM control bit is asserted. (When writeM==0, any value may + * appear in outM). The outM and writeM outputs are combinational: + * they are affected instantaneously by the execution of the current + * instruction. The addressM and pc outputs are clocked: although they + * are affected by the execution of the current instruction, they commit + * to their new values only in the next time step. If reset==1 then the + * CPU jumps to address 0 (i.e. pc is set to 0 in next time step) rather + * than to the address resulting from executing the current instruction. + */ + +CHIP CPU { + + IN inM[16], // M value input (M = contents of RAM[A]) + instruction[16], // Instruction for execution + reset; // Signals whether to re-start the current + // program (reset==1) or continue executing + // the current program (reset==0). + + OUT outM[16], // M value output + writeM, // Write to M? + addressM[15], // Address in data memory (of M) + pc[15]; // address of next instruction + + PARTS: + // D register + // write to D iff opcode is 1 (C-instruction) and d2 is 1 (destination includes D) + And(a=instruction[15], b=instruction[4], out=loadD); + DRegister(in=aluout, load=loadD, out=aluX); + // A register, mux'd with M + Mux16(a=instruction, b=aluout, sel=instruction[15], out=inA); + Not(in=instruction[15], out=isAinst); // is A-instruction + // write to A iff opcode is 0 (A-instruction) or d1 is 1 (destination includes A) + Or(a=isAinst, b=instruction[5], out=loadA); + ARegister(in=inA, load=loadA, out=outA, out[0..14]=addressM); + Mux16(a=outA, b=inM, sel=instruction[12], out=aluY); // depends on the `a` bit in C-instruction + // ALU + ALU( + x=aluX, y=aluY, + zx=instruction[11], nx=instruction[10], + zy=instruction[9], ny=instruction[8], + f=instruction[7], no=instruction[6], + out=aluout, zr=zr, ng=ng, out=outM + ); + // write to M iff opcode is 1 (C-instruction) and d3 is 1 + And(a=instruction[15], b=instruction[3], out=writeM); + // PC and jump conditions + Or(a=ng, b=zr, out=ngzr); + Not(in=ngzr, out=po); // ALU output is positive + And(a=instruction[2], b=ng, out=lt); + And(a=instruction[1], b=zr, out=eq); + And(a=instruction[0], b=po, out=gt); + Or(a=lt, b=eq, out=le); + Or(a=le, b=gt, out=jmp); + // write A to PC iff opcode is 1 (is C-instruction) and at least one specified jump condition is satisfied + And(a=instruction[15], b=jmp, out=loadPC); + PC(in=outA, load=loadPC, inc=true, reset=reset, out[0..14]=pc); +} -- cgit v1.2.3