summaryrefslogtreecommitdiff
path: root/projects/hack-vm/arith_logic.py
diff options
context:
space:
mode:
authorFrederick Yin <fkfd@fkfd.me>2022-08-22 17:04:19 +0800
committerFrederick Yin <fkfd@fkfd.me>2022-08-22 17:04:19 +0800
commit10c9f64f592198d78aad11ebc676629d92ca6576 (patch)
tree1b4f8a21c72dae1700d92892a619ad9ddaf25cbf /projects/hack-vm/arith_logic.py
parent900bd8fe1934f83ea35ab8673dda5239ae2dfca8 (diff)
Project 07: VM translator part 1
Diffstat (limited to 'projects/hack-vm/arith_logic.py')
-rw-r--r--projects/hack-vm/arith_logic.py26
1 files changed, 26 insertions, 0 deletions
diff --git a/projects/hack-vm/arith_logic.py b/projects/hack-vm/arith_logic.py
new file mode 100644
index 0000000..6716ad9
--- /dev/null
+++ b/projects/hack-vm/arith_logic.py
@@ -0,0 +1,26 @@
+from .utils import *
+
+# common preamble to add, sub, and, or
+BINARY_COMMON_ASM = """@SP
+AM=M-1
+D=M
+A=A-1
+"""
+
+# common preamble to neg and not
+UNARY_COMMON_ASM = """@SP
+A=M-1
+"""
+
+ARITH_LOGIC_ASM = {
+ "add": BINARY_COMMON_ASM + "M=D+M\n",
+ "sub": BINARY_COMMON_ASM + "M=M-D\n",
+ "and": BINARY_COMMON_ASM + "M=D&M\n",
+ "or": BINARY_COMMON_ASM + "M=D|M\n",
+ "neg": UNARY_COMMON_ASM + "M=-M\n",
+ "not": UNARY_COMMON_ASM + "M=!M\n",
+}
+
+
+def translate_arith_logic(command):
+ return ARITH_LOGIC_ASM[command]