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+// This file is part of www.nand2tetris.org
+// and the book "The Elements of Computing Systems"
+// by Nisan and Schocken, MIT Press.
+// File name: projects/03/b/RAM16K.hdl
+
+/**
+ * Memory of 16K registers, each 16 bit-wide. Out holds the value
+ * stored at the memory location specified by address. If load==1, then
+ * the in value is loaded into the memory location specified by address
+ * (the loaded value will be emitted to out from the next time step onward).
+ */
+
+CHIP RAM16K {
+ IN in[16], load, address[14];
+ OUT out[16];
+
+ PARTS:
+ DMux4Way(in=load, sel=address[12..13], a=l0, b=l1, c=l2, d=l3);
+ RAM4K(in=in, load=l0, address=address[0..11], out=o0);
+ RAM4K(in=in, load=l1, address=address[0..11], out=o1);
+ RAM4K(in=in, load=l2, address=address[0..11], out=o2);
+ RAM4K(in=in, load=l3, address=address[0..11], out=o3);
+ Mux4Way16(a=o0, b=o1, c=o2, d=o3, sel=address[12..13], out=out);
+}